DSPIC30F2010T-20I/SO【PDF 7/66 页】IC DSPIC MCU/DSP 12K 28SOIC

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2010 Microchip Technology Inc.

DS70102K-page 15

dsPIC30F Flash Programming Specification

SSS<2:0>

FSS

Secure Segment Program Memory Code Protection (only present in

dsPIC30F5011/5013/6010A/6011A/6012A/6013A/6014A/6015)

111 = No Secure Segment

110 = Standard security; Small-sized Secure Program Flash

[Secure Segment starts after BS and ends at 0x001FFF]

101 = Standard security; Medium-sized Secure Program Flash

[Secure Segment starts after BS and ends at 0x003FFF]

100 = Standard security; Large-sized Secure Program Flash

[Secure Segment starts after BS and ends at 0x007FFF]

011 = No Secure Segment

010 = High security; Small-sized Secure Program Flash

[Secure Segment starts after BS and ends at 0x001FFF]

001 = High security; Medium-sized Secure Program Flash

[Secure Segment starts after BS and ends at 0x003FFF]

000 = High security; Large-sized Secure Program Flash

[Secure Segment starts after BS and ends at 0x007FFF]

SWRP

FSS

Secure Segment Program Memory Write Protection (only present in

dsPIC30F5011/5013/6010A/6011A/6012A/6013A/6014A/6015)

1 = Secure Segment program memory is not write-protected

0 = Secure program memory is write-protected

GSS<1:0>

FGS

General Segment Program Memory Code Protection (only present in

dsPIC30F5011/5013/6010A/6011A/6012A/6013A/6014A/6015)

11 = Code protection is disabled

10 = Standard security code protection is enabled

0x = High security code protection is enabled

GCP

FGS

General Segment Program Memory Code Protection (present in all devices

except dsPIC30F5011/5013/6010A/6011A/6012A/6013A/6014A/6015)

1 = General Segment program memory is not code-protected

0 = General Segment program memory is code-protected

GWRP

FGS

General Segment Program Memory Write Protection

1 = General Segment program memory is not write-protected

0 = General Segment program memory is write-protected

BKBUG

FICD

Debugger/Emulator Enable

1 = Device will reset into Operational mode

0 = Device will reset into Debug/Emulation mode

COE

FICD

Debugger/Emulator Enable

1 = Device will reset into Operational mode

0 = Device will reset into Clip-on Emulation mode

ICS<1:0>

FICD

ICD Communication Channel Select

11 = Communicate on PGC/EMUC and PGD/EMUD

10 = Communicate on EMUC1 and EMUD1

01 = Communicate on EMUC2 and EMUD2

00 = Communicate on EMUC3 and EMUD3

RESERVED FBS, FSS, FGS Reserved (read as ‘1’, write as ‘1’)

—All

Unimplemented (read as ‘0’, write as ‘0’)

TABLE 5-7:

CONFIGURATION BITS DESCRIPTION (CONTINUED)

Bit Field

Register

Description

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